1. Field of the Invention
The present invention relates to a .DELTA..SIGMA. (delta-sigma) modulator, DA converter and AD converter, and, more particularly, relates to an improvement with which a noise-shaping equal to that of a multi-bit higher-order modulator required for improved accuracy is realized on a small-scale circuit while retaining stability.
2. Description of the Background Art
Presently, converters equipped with .DELTA..SIGMA. modulator are widely used as a high-precision DA converter or AD converter having a resolution over 14 bits. In a DA or AD converter having a .DELTA..SIGMA. modulator, a quantization with a small number of bit, such as 1-bit quantization, is performed while a folding noise and quantization noise are reduced by oversampling (for example, when handling voice signals, sampling is performed by an-integral multiple of the inherent sampling frequency, e.g., 44.1 kHz) and noise-shaping (i.e., the frequency characteristic of a quantization noise inherently flat is more enhanced at a higher frequency band).
FIGS. 13 and 14 are block diagrams showing the configurations of conventional DA converter and AD converter, each having a .DELTA..SIGMA. modulator, respectively. In the DA converter 151 shown in FIG. 13, an inputted digital signal ID is converted while it passes through an interpolation filter 70, .DELTA..SIGMA. modulator 71, internal DA conversion circuit and lowpass filter 73 in this order, and then outputted as an analog signal OA. The .DELTA..SIGMA. modulator 71 has in a feedback loop thereof (i.e., a signal transmission path in which a signal circulates through the input, the output, and the input) an integrator 76, quantizer 77 and delay circuit 78. For enabling feedback, an arithmetic operation unit 75 that serves as a substracter is provided at the intersection between the input line and feedback loop. The delay circuit 78 may be placed in anywhere within the feedback loop.
In the AD converter 152 shown in FIG. 14, an inputted analog signal IA is converted while it passes through an anti-aliasing filter 80, .DELTA..SIGMA. modulator 81 and decimation filter 82 in this order, and then outputted as a digital signal OD. The .DELTA..SIGMA. modulator 81 has in a feedback loop thereof an integrator 86, quantizer 87, delay circuit 88 and internal DA conversion circuit 89. For enabling feedback, an arithmetic operation unit 85 is provided at the intersection between the input line and feedback loop. The delay circuit 88 may be placed in anywhere within the feedback loop.
Since in the feedback loop of the .DELTA..SIGMA. modulator 71, digital signals are regarded as a processing object, all the circuits within the loop are configured as a digital circuit. Whereas in the feedback loop of the .DELTA..SIGMA. modulator 81, except for a signal transmission path from the output of the quantizer 87 to the input of the internal DA conversion circuit 89, analog signals are regarded as a processing object. Therefore, all the circuits within the feedback loop, except for the signal transmission path from the output of the quantizer 87 to the input of the internal DA conversion circuit 89, are configured as an analog circuit.
In the DA converter 151 and AD converter 152, their signal conversion accuracy as a whole, depends upon the accuracy of signal conversion in the .DELTA..SIGMA. modulators 71 and 81, respectively. To increase the conversion accuracy of the .DELTA..SIGMA. modulators 71 and 81, there have been known conventionally a method of increasing the order (order increasing method) and a method of increasing the number of output bit of a quantizer (multi-bit method). FIG. 15 is a block diagram showing an example where the order increasing method is applied. FIG. 16 is a block diagram showing an example where the multi-bit method is applied in addition to the order increasing method.
A quantizer 77 of a .DELTA..SIGMA. modulator 71a in FIG. 15 is an 1-bit quantizer, and a quantizer 79 of a .DELTA..SIGMA. modulator 71b in FIG. 16 is a multi-bit quantizer. In both .DELTA..SIGMA. modulators 71a and 71b, their feedback loops are branched into four, and one to four integrators 76 are interposed in each branch. That is, the .DELTA..SIGMA. modulator 71a is configured as an 1-bit fourth-order modulator, and the .DELTA..SIGMA. modulator 71b is configured as a multi-bit fourth-order modulator. The relationship between input signal X and output signal Y in the .DELTA..SIGMA. modulators 71a and 71b is expressed by using z conversion which is effective in describing a sample data control system, as follows:
Signals A to C, and Y in FIGS. 15 and 16 are expressed by the following formulas 1 to 4, respectively: EQU A=(X-z.sup.-1 Y)/(1-z.sup.-1) (1); EQU B=(A-z.sup.-1 Y)/(1-z.sup.-1) (2); EQU C=(B-z.sup.-1 Y)/(1-z.sup.-1) (3);
and EQU Y=(C-z.sup.-1 Y)/(1-z.sup.-1)+e (4)
wherein e is a quantizing error in the quantizer 77 or 79. From these formulas, there is obtained: EQU Y=X+(1-z.sup.-1).sup.4 e (5)
Formula 5 shows that in the .DELTA..SIGMA. modulators 71a and 71b, a quantization noise e contributes to an output signal Y in the form proportional to the fourth-order differential coefficient of fourth order of the quantization noise e. Since the frequency characteristic of the quantization noise e is flat, the frequency characteristic of the fourth-order differential coefficient of the quantization noise e is expressed by the fourth-order function of frequency. Specifically, Formula 5 shows that, according to the fourth-order function, the influence of the quantization noise e on the output signal Y increases as frequency increases.
Thus in a higher-order modulator, the quantization noise e is minimized in a low frequency band whereas it is enhanced in a high frequency band, based on the function of higher order of frequency. Namely, noise-shaping is enhanced based on the function of fourth order of frequency. From the interpolation filter 70, the input signal X obtained by oversampling is inputted to the .DELTA..SIGMA. modulator 71, thereby the quantization noise e in the inherently required low frequency band (e.g., a band of not more than 44.1 kHz is required in voice signal processing) can be reduced effectively.
In addition, the quantization noise e itself is reduced by multi-bit method. Specifically, the quantization noise e reduces as the number of output bit of a quantizer is higher. In the .DELTA..SIGMA. modulator 71b, the number of bit of the quantizer 79 is larger than that of the quantizer 77 in the .DELTA..SIGMA. modulator 71a. Thereby, the quantization noise component in Formula 5 is lowered by that amount in the .DELTA..SIGMA. modulator 71b.
The foregoing is true for the .DELTA..SIGMA. modulator 81 as well. FIG. 17 is a block diagram illustrating an example where the order increasing method and multi-bit method are applied to the .DELTA..SIGMA. modulator 81, to obtain a .DELTA..SIGMA. modulator 81a. A quantizer 90 of the .DELTA..SIGMA. modulator 81a in FIG. 17 is a multi-bit quantizer. The feedback loop of the .DELTA..SIGMA. modulator 81a is branched into two, and one to two integrators 86 are interposed in each branch. That is, the .DELTA..SIGMA. modulator 81a is configured as a multi-bit second-order modulator. The relationship between input signal X and output signal Y in the .DELTA..SIGMA. modulator 81a is expressed as follows:
Signals D and Y in FIG. 17 are expressed as follows: EQU D=1/(1-z.sup.-1).multidot.(X-z.sup.-1 Y-e.sub.D) (6);
and EQU Y=1/(1-z.sup.-1).multidot.(D-z.sup.-1 Y-e.sub.D)+e (7),
respectively,
wherein e is a quantization error in the quantizer 90, and e.sub.D is a conversion error in the internal DA conversion circuit 89.
From Formulas 6 and 7, the signal Y is expressed as follows: EQU Y=X-e.sub.D -(1-z.sup.-1)e.sub.D +(1-z.sup.-1).sup.2 e (8)
Formula 8 shows that in the .DELTA..SIGMA. modulator 81a, a quantization noise e contributes to an output signal Y in the form proportional to the second-order differential coefficient of the quantization noise e. Accordingly, in the .DELTA..SIGMA. modulator 81a, noise-shaping is enhanced based on the second-order function of frequency. As described, in the .DELTA..SIGMA. modulators 71 and 81, conversion accuracy can be increased by the order increasing method and multi-bit method.
Unfortunately, it is known that the order increasing method presents the problem of reduction in the stability of a .DELTA..SIGMA. modulator. In general, it is difficult, they say, to obtain stability in a modulator of three-order or more. Although it is known that the multi-bit method can improve stability, it is necessary to prepare a DA conversion circuit corresponding to a multi-bit, as the internal DA conversion circuits 72 and 89 of the converters 151 and 152, respectively. It is also known that it is not easy to form uniform elements (not shown) which are provided such as to correspond to a multi-bit in the internal DA conversion circuits 72 and 89, respectively, and that a mismatch (non-uniformity) between the elements deteriorates conversion accuracy. To avoid deterioration of conversion, a randomizer that selects at random the elements constituting the internal DA conversion circuits 72 and 89, is required to be disposed at the preceding stage of the elements. This causes the problem that circuit scale is increased.